Conventional methods of forming integrated circuit devices may include steps to form single and/or dual damascene structures using copper (Cu) as an electrical interconnect material. As illustrated by FIGS. 1A-1E, a conventional damascene process may utilize a multi-layered mask structure to support selective etching of one or more underlying dielectric layers. In particular, FIG. 1A illustrates steps to form a relatively porous low-k inter-layer dielectric (ILD) layer 12 on an underlying dielectric layer 10, which may be a inter-metal dielectric (IMD) layer. This low-k ILD layer 12 may be formed of a material, such as SiCOH, which has a dielectric constant less than a dielectric constant of silicon dioxide (SiO2). FIG. 1A also illustrates steps to form a multi-layered mask (MLM) layer on the ILD layer 12. This multi-layered mask layer is illustrated as including a hard mask layer 14 (e.g., SiO2 layer), an organic planarization layer (OPL) 16, a low temperature oxide (LTO) layer 18, an antireflective coating (ARC) 20 and a patterned photoresist (PR) layer 22. As illustrated by FIG. 1B, a selective etching step is performed to etch through the antireflective coating 20, the LTO layer 18 and the OPL layer 16 in sequence using the patterned photoresist layer 22 as an etching mask. The patterned photoresist layer 22 and the antireflective coating 20 are then removed.
Referring now to FIGS. 1C-1D, another selective etching step is performed to etch through and form a via opening within the hard mask layer 14 and the ILD layer 12 and define a recess within the IMD layer 10, using the patterned OPL layer 16 as an etching mask. The patterned OPL layer 16 is then removed. This OPL layer 16 may be removed using an ashing process that is performed in an oxygen ambient. Unfortunately, this ashing process may operate to convert sidewall portions of a SiCOH-type ILD layer 12, which are exposed to the ashing process, into silicon dioxide. This conversion process may occur in response to the removal of carbon (C) and hydrogen (H) atoms from the ILD layer 12. Thereafter, as illustrated by FIG. 1E, a cleaning process using a diluted hydrofluoric acid (DHF) solution may cause an undercutting (i.e., recession) of the sidewalls of the ILD layer 12 relative to the hard mask layer 14 because DHF operates as an etchant to silicon dioxide. This undercutting of the sidewalls of the ILD layer 12 may result in the formation of voids within an electrically conductive via (e.g., copper plug, not shown) that is subsequently formed within the opening in the hard mask layer 14 and the ILL) layer 12. The formation of such voids may result in reduced device yield by reducing the reliability of electrical interconnects within an integrated circuit chip.